Due to their structural simplicity, DRAMs (dynamic random access memories) can provide more memory per unit chip area than other types of memories such as static random access memories. A DRAM is comprised of a plurality of DRAM cells, each of which includes a capacitor for storing information and a transistor coupled to the capacitor for regulating when the capacitor is charged or discharged. During a read operation, a word line is asserted, turning on the transistor. The enabled transistor allows the voltage across the capacitor to be read by a sense amplifier through a bit line. During a write operation, the data to be written is provided on the bit line while the word line is asserted.
To satisfy the demand for greater memory storage, there is a need for DRAM memory cells of reduced size. DRAM memory cell size can be reduced in several ways. One way is to reduce the minimum feature size of a DRAM memory cell through the advances in process technology. Another way to reduce the size of a DRAM memory cell is by designing a memory cell having a smaller feature size. For example, many DRAM chips on the market today have a memory cell size of 6F2, where F stands for the photolithographic minimum feature width.
However, the decrease of the size of memory cells results in some issues. The disturbance between memory cells or between word lines may easily occur and the resistance of the word line increases due to the decrease of its cross-sectional area.
One conventional DRAM device includes an array having a plurality of access transistors. A word line functioning as a gate extends from one side of the array to an opposite side of the array such that each transistor can operate as a double gate transistor. Due to the resistance of the word line, the voltage supplied to the word line drops along the word line. Consequently, two corresponding locations on the opposite sides of the array have significant voltage drop, resulting in problematic operation of to the corresponding access transistor.